The exemplary embodiments relate to enhancement of a via's reliability and, more particularly, relate to a structure and method of enhancing the reliability of vias by making the bottom of the vias be under compressive stress.
In a semiconductor structure, vias may be the weakest link for interconnect reliability. In the latest semiconductor technology, vias are smaller and so are more susceptible to voids and opens. Under the ground rules for the latest semiconductor technology, there may not be room for redundant vias so there may be only one via, an “iso-via”, that provides the connection between wiring levels. Due to the lack of redundancy, any iso-via failure can cause a circuit, or even the entire semiconductor chip, to fail.